
`define RST_500MS_CNT 'd6250000
`define DIVIDE_LINE_COLOR   16'h001f
 `define LOONGSON_BACK_COLOR 16'b01000_010000_01000  //red:8,green:16,blue:8
 `define LOONGSON_COLOR      16'b11111_000000_00000  //red
module lcd_init(
    input clk,
    input rst_n,

    output          lcd_rst_n,
    output          lcd_rs,
    output          lcd_wr_n,
    output [15:0]   lcd_db,
    output logic    init_end
);

logic [23:0] delay_timer;
logic start_init;
logic delay_120ms_valid;
logic init_rs_part;
logic [23:0] init_rom_pc;
logic [23:0] init_rom_data;
logic lcd_rst_n_r;
logic init_display_begin;
reg [4:0] display_x_l;   //base-24
reg [4:0] display_x_h;
reg [9:0] display_y;
logic [15:0] display_data;

assign lcd_rst_n = lcd_rst_n_r;
assign lcd_wr_n = ~start_init | delay_120ms_valid;
assign lcd_rs   = init_rs_part;
assign lcd_db   = init_rom_pc == 11'd1882 ? 16'h2900 :
                  init_rom_pc == 11'd1883 ? 16'h2c00 :
                  init_display_begin ? display_data :
                  init_rs_part ? {8'h00, init_rom_data[7:0]} : 
                               init_rom_data[23:8];

always_ff @(posedge clk or negedge rst_n)begin
    if(~rst_n)begin
        delay_timer <= 0;
        init_end <= 1'b0;
        start_init <= 1'b0;
        delay_120ms_valid <= 1'b0;
        init_rom_pc <= 0;
        init_rs_part <= 0;
        lcd_rst_n_r <= 0;
        init_display_begin <= 0;
    end
    else begin
        if(delay_timer != `RST_500MS_CNT)begin
            delay_timer <= delay_timer + 1;
        end
        if(delay_timer == `RST_500MS_CNT)begin
            start_init <= 1'b1;
        end
        if(&delay_timer[21:19])begin
            lcd_rst_n_r <= 1'b1; // 500ms后LCD复位
        end
       // 5510 IC delay逻辑
        if (init_rom_pc==11'd381 && !init_rs_part)begin
          delay_120ms_valid <= 1'b1;
        end
        else if ((init_rom_pc==11'd1881) && !init_rs_part)begin
          delay_120ms_valid <= 1'b0;
        end

        if(!init_rs_part && start_init & ~init_end)begin
            init_rom_pc <= init_rom_pc + 1'b1;
        end
        if(init_display_begin)begin
            init_rs_part <= 1'b1;
        end
        else if(start_init & ~init_end)begin
            init_rs_part <= ~init_rs_part;
        end

        // if(init_rom_pc == 11'd1882)begin
        //     init_end <= 1'b1;
        // end
        if((display_x_h==5'd19 && display_x_l==5'd23) && (display_y==10'd799))begin
            init_end <= 1'b1;
        end
        if(init_rom_pc == 11'd1883)begin
            init_display_begin <= 1'b1;
        end
    end
end


assign display_data = 16'hffff;


always @(posedge clk)   //display_x and display_y
begin
  if (!start_init || init_end)
  begin
    display_x_l <= 5'd0;
  end
  else if ( init_display_begin )
  begin
    if (display_x_l == 5'd23)
    begin
      display_x_l <= 5'd0;
    end
    else
    begin
      display_x_l <= display_x_l + 1'b1;
    end
  end

  if (!start_init || init_end)
  begin
    display_x_h <= 5'd0;
  end
  else if ( init_display_begin )
  begin
    if (display_x_l == 5'd23)
    begin
      if (display_x_h==5'd19)
      begin
        display_x_h <= 5'd0;
      end
      else
      begin
        display_x_h <= display_x_h + 1'b1;
      end
    end
  end

  if (!start_init || init_end)
  begin
    display_y <= 10'd0;
  end
  else if ( display_x_h==5'd19 && display_x_l==5'd23 )
  begin
    display_y <= display_y + 1'b1;
  end
end

rom_5510 rom (
    .clka(clk),
    .addra(init_rom_pc[9:0]),
    .douta(init_rom_data)
);


endmodule